Leveraging the Variation Tolerance of Latches

Deterministic worst-case timing analysis has been demonstrated to provide an unnecessarily large timing margin for process variations. We show that this overconservatism penalizes designs implemented with levelsensitive state elements more than equivalent designs using edge-triggered elements. Under this model, when retiming and/or clock skew scheduling are applied, the optimal period in both latchand flip-flop-based designs is limited by the maximum mean delay of any cycle in the circuit. However, latch-based designs are often dramatically more variationtolerant, resulting in a better yield and/or allowing more aggressive performance. We employ a statistical latch analysis to quantify this effect in several benchmark circuits, and show a straightforward and scalable technique to further improve the tolerance of latches to variation. The technique facilitates an exchange of criticality between setup and hold timing constraints. The yield-optimized latch-based designs result in an average 7.7 times fewer failures than the unscheduled designs that meet the same deterministic timing constraints.